American Semiconductor Inc
- View government funding actions
- Boise, ID 837057368
- Phone: 208-336-2773
- Corporate URL: www.americansemi.com
- Estimated Number of Employees: 18
- Estimated Annual Receipts: $3,323,624
- Business Start Date: 2001
- Contact Person: Douglas Hackler
- Contact Phone: 208-336-2773
- Contact Email: doughackler@americansemi.com
- Business Structure:
- Corporate Entity (Not Tax Exempt)
- Business Type:
- For Profit Organization
- Manufacturer of Goods
- Industries Served: Bare Printed Circuit Board Manufacturing, Semiconductor and Related Device Manufacturing, Engineering Services
- Product Areas: ADP SOFTWARE, INFORMATION TECHNOLOGY SOFTWARE, TECHNOLOGY STUDIES, SPECIAL STUDIES/ANALYSIS- TECHNOLOGY, ADP SYSTEMS ANALYSIS SERVICES, IT AND TELECOM- SYSTEMS ANALYSIS, PROGRAMMING SERVICES, IT AND TELECOM- PROGRAMMING, IT AND TELECOM- INTEGRATED HARDWARE/SOFTWARE/SERVICES SOLUTIONS, PREDOMINANTLY SERVICES, IT AND TELECOM- ANNUAL SOFTWARE MAINTENANCE SERVICE PLANS, TECH REP SVCS/ADP EQ & SUPPLIES, TECHNICAL REPRESENTATIVE- ADP EQUIPMENT/SOFTWARE/SUPPLIES/SUPPORT EQUIPMENT
Sampling of Federal Government Funding Actions/Set Asides
In order by amount of set aside monies.
- $374,365 - Tuesday the 1st of May 2012
Department Of Air Force
FA9453 DET 8 AFRL PKV8
HIGH PERFORMANCE, ULTRA LOW POWER SPA-1 ASIC FOR SPACE PLUG-AND-PLAY AVIONICS - $149,990 - Friday the 20th of April 2012
Department Of Air Force
FA8650 USAF AFMC AFRL/RQK
STRUCTURALLY COMPLIANT RF ELECTRONICS-SBIR I - $124,926 - Friday the 4th of January 2013
National Aeronautics And Space Administration
NASA SHARED SERVICES CENTER
THE PROPOSED 45 NM RADIATION HARDENED PLATFORM BASED STRUCTURED ASIC ARCHITECTURE OFFERS THE PERFORMANCE AND DENSITY EXPECTED OF A CUSTOM ASIC WITH THE LOW MANUFACTURING COST ASSOCIATED WITH A STRUCTURED ASIC. THE LOW COST, HIGH PERFORMANCE CUSTOMIZATION OF THE STRUCTURED ASIC PORTION OF THE CHIP IS MADE POSSIBLE BY THE 1-D 45 NM MASK-LITE PROCESS TECHNOLOGY. THE CHIP ARCHITECTURE IS OPTIMIZED FOR SENSOR DATA HANDLING APPLICATIONS IN SPACE AND THE DESIGN PROCESS PROVIDES FOR A SHORT DEVELOPMENT SCHEDULE. THE ARCHITECTURE PROVIDES A HARD MACRO MICROCONTROLLER CORE WITH VIA-ROM PROGRAM MEMORY, SRAM DATA MEMORY, CPU SUPPORT LOGIC, AN APPROPRIATE SET OF ANALOG FUNCTIONS, AND A STRUCTURED ASIC SECTION FOR APPLICATION SPECIFIC FUNCTIONALITY. A RAD-HARD BY DESIGN LOGIC CELL LIBRARY IS PROVIDED FOR THE STRUCTURED ASIC AREA OF THE DIE ALONG WITH A NUMBER OF PRE-COMPILED MACRO FUNCTIONS SUCH AS TIMERS AND SERIAL I/O TO REDUCE DEVELOPMENT TIME. THE 1-D MASK-LITE PROCESS PROVIDES A DRAMATIC REDUCTION IN THE MASK COST, ALLOWING LOWER VOLUME DESIGNS TO GAIN ACCESS TO 45 NM TECHNOLOGY, AND PROVIDES PERFORMANCE IMPROVEMENT OVER CONVENTIONAL VIA MASK STRUCTURED ASIC TECHNOLOGIES BY ELIMINATING METAL LAYER STUBS. STANDARD LOGIC DESIGN, VERIFICATION AND LAYOUT EDA TOOLS ARE USED TO COMPLETE A CHIP DESIGN. THE FIXED MICROCONTROLLER PLATFORM PORTION OF THE CHIP IS IMPLEMENTED WITH OPTIMIZED STANDARD CELLS RATHER THAN THE STRUCTURED ASIC LOGIC CELLS, RESULTING IN STANDARD ASIC PERFORMANCE LEVELS FOR THE CORE LOGIC.
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